The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Application No. 2000-4086 filed on Jan. 27, 2000, and which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a method of forming contact holes of a semiconductor device, in particular, forming contact holes of a semiconductor device so that damage at a field oxide layer can be prevented and processing yield can be increased as a result.
2. Description of the Related Art
In order to reduce a layout area at a portion of a chip occupying a large-area, such as a CMOS memory cell, pattern sizes and intervals between patterns should be reduced in line with the increase of the integration degree. In particular, distance between gate electrodes should also be reduced so that contacts can be formed by utilizing a self aligned contact method by which a contact overlaps the gate electrode over the gate electrode region, to reduce the total layout area. In order to apply the self aligned contact method, an insulation layer that has an etching-resistance while being etched to form a contact hole, is formed on the gate electrode. The insulation layer prevents a short with the gate electrode formed from polysilicon material. Spacers also should be provided on both sides of the gate electrode. Furthermore, spacers are formed to isolate a heavily doped region from a conductive layer of the gate electrode when an LDD type MOS transistor is formed.
In general, the thickness of the spacer for forming the LDD type transistor depends on the characteristics of the transistor. As the integration degree of a semiconductor device is increased, the distance between the gate electrodes is decreased to twice the thickness of the spacer. Insulating spacers provided on both side walls of the gate electrode should remain after implementing an etching process for forming a contact hole by applying a self aligned contact method. Therefore, a contact region with an active region of a semiconductor substrate depends on the thickness of the spacer, regardless of the pattern shapes of the gate electrodes.
Accordingly, if the spacers are formed too thickly, the exposed portion of the active region becomes too narrow. In addition, when a dry etching process is implemented on this narrow active region, the etching can stop to form an incompletely etched hole, or it can stop to form a wiring layer having high resistivity, thereby inducing a defect. Furthermore, it is difficult to fill this narrow contact hole with a wiring layer having low resistivity.
U.S. Pat. No. 5,763,312 by Jeng et al. discloses a method of fabricating a semiconductor device having LDD spacers using double spacers. FIGS. 1A-1F are crosssectional views explaining a method of forming the LDD spacers illustrated in U.S. Pat. No. 5,763,312.
Referring to FIG. 1A, a gate electrode 10 including a gate oxide layer 4, a conductive pattern 6 and a first insulating pattern 8 is formed on an active region of a semiconductor substrate 1 which is separated into an active region and a field region by a field oxide layer 2.
Referring to FIG. 1B, a first impurity doped region 12 is formed on the semiconductor substrate 1 by doping impurities having a low concentration using the gate electrode 10 as a mask.
Referring to FIG. 1C, a second insulating layer (not shown) is formed by blanket depositing an insulating material, preferably silicon nitride, on the semiconductor substrate to a thickness of about 400-800 xc3x85 through a chemical vapor deposition method. Then, the second insulating layer is etched back to form first spacers 14 on the side walls of gate electrode 10. The thickness of first spacers 14 is about 300-700 xc3x85.
Referring to FIG. 1D, a third insulating layer (not shown) is formed by blanket depositing an insulating material, preferably silicon oxide, to a thickness of about 400-1000 xc3x85 through a chemical vapor deposition method on the semiconductor substrate on which the gate electrode 10 and first spacers 14 are formed. Then, the third insulating layer is etched back to form second spacers 16 on first spacers 14. The thickness of second spacers 16 is about 200-800 xc3x85.
Referring to FIG. 1E, a second impurity doped region 18 is formed within the first impurity doped region 12 after forming second spacers 16 by doping impurities of high concentration into the semiconductor substrate 1 using gate electrode 10, first spacers 14 and second spacers 16 as masks.
Referring to FIG. 1F, a fourth insulating layer (not shown) is formed on the semiconductor substrate 1. The fourth insulating layer is formed by blanket depositing BPSG (Boro-Phosphosilicate Glass) or PSG (Phosphosilicate Glass) to a thickness of about 3,000-10,000 xc3x85 through a low pressure chemical vapor deposition method or a PECVD (Plasma Enhanced Chemical Vapor Deposition Method).
Next, a mask pattern (not shown) is formed on the fourth insulating layer to form contact holes. Then, the fourth insulating layer is etched by using the mask pattern as an etching mask to form contact holes in order to expose the surface of the semiconductor substrate 1 including first and second impurity doped regions 12 and 18.
However, according to the method of forming the LDD spacers of the semiconductor device, the third insulating layer and the field oxide layer are formed from the same or similar materials. As a result, the etching ratios of the third insulating layer and the field oxide layer are identical or similar. Accordingly, a problem occurs in that a portion of the field oxide layer may be etched during implementation of the etch back process on the third insulating layer to form the second spacers. When this portion of the field oxide layer is etched, the ability of the field oxide layer to isolate each cell is reduced, thus leading to erroneous operation of the manufactured device.
Recently, the width of a contact hole has been reduced as an integration degree of semiconductor device has increased. However, the reduction of the width of the contact hole is limited. To solve this problem, a method of forming a non-overlapping contact or a borderless contact has been developed. Through this method, a distance between the contact hole and the gate electrode is kept constant while the size of the contact hole is not reduced. The contact hole is formed to overlie both active and field oxide regions.
Initially, a borderless contact method is applied by etching an interlayer dielectric formed on a semiconductor substrate to expose a portion of a field oxide layer and an adjacent surface portion of the semiconductor substrate. However at this time, a problem of forming a recess on the exposed field oxide layer is generated. That is, the depth of the recess is deeper than a source/drain junction of an active region, or is near a junction boundary, and thus a path of direct contact between a contact that is formed afterward and the semiconductor substrate results. This will induce a current leakage.
In addition, even if the contact hole is shallower than the source/drain junction of the active region, Ti and TiN which are applied to form a barrier layer during a process of forming a contact that is implemented afterward, react with silicon at the source/drain region during a heat treatment, if the contact hole is formed near the junction. When Ti and TiN react with silicon, a conductive silicide layer is formed to generate a current leakage.
In order to solve the above-described problem, a method of forming an etch stopping layer to stop an etching process for formation of a contact hole and to prevent a recess of a field oxide layer from being formed, is disclosed in U.S. Pat. No. 5,652,176 by Maniar et al. FIGS. 2A to 2D are cross-sectional views explaining the conventional method of forming a borderless contact.
Referring to FIG. 2A, a mask pattern is formed on a semiconductor substrate 30 and a trench is formed by etching semiconductor substrate 30 using the mask pattern as an etching mask. The depth of the trench from the surface of semiconductor substrate 30 is about 4,000-6,000 xc3x85 and the width of that is about 4,000-6,000 xc3x85. Next, the mask pattern formed on the surface of the semiconductor substrate is removed and an oxide material is blanket deposited on the semiconductor substrate with a thickness that is sufficient enough to fill the trench. Silicon oxide, TEOS (Tetra-Ethyl-Ortho-Silicate), and the like can be used for the oxide material, and a chemical vapor deposition method is preferred. Subsequently, a planarization process is implemented until semiconductor substrate 30 is exposed to form a field oxide layer 32 within semiconductor substrate 30. Then, semiconductor substrate 30 is separated into an active region and a field region by field oxide layer 32.
Referring to FIG. 2B, a gate electrode including a gate oxide layer 34, a conductive pattern 36 and a capping layer pattern 38 is formed on the active region of semiconductor substrate 30. Then, a common ion doping process is implemented by using the gate electrode as a mask to form a first impurity region 40 within semiconductor substrate 30. Subsequently, an insulating material is deposited on semiconductor substrate 30 and it is etched back to form spacers 42 on the side walls of the gate electrode. Then, a second impurity region 44 is formed within semiconductor substrate 30 by implementing a common ion doping process and using spacers 42 as a mask.
Referring to FIG. 2C, an etch stopping layer 46 is formed by blanket depositing silicon nitride on the whole surface of semiconductor substrate 30. Etch stopping layer 46 functions to protect field oxide layer 32 during the subsequent etching process. Then, an interlayer dielectric 48 is formed on the semiconductor substrate 30 on which etch stop layer 46 is formed. The interlayer dielectric 48 is formed by blanket depositing an insulating material such as silicon oxide, BPSG or PSG to a thickness of about 3,000-10,000 xc3x85 through a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method.
Referring to FIG. 2D, a photoresist pattern (not shown) is formed on the interlayer dielectric 48 using a common photolithography. Then, the interlayer dielectric 48 and etch stopping layer 46 are successively etched by using the photoresist pattern as an etching mask to expose a portion of the surface of the semiconductor substrate 30 from a portion of field oxide layer 32 to a portion of the gate electrode that is adjacent to the field oxide layer 32, and to form a contact hole which forms the borderless contact.
However, the above-described borderless contact method and a self aligned contact method by which spacers are formed on the sidewalls of the gate electrode are used as processing margins, so the two methods cannot be applied simultaneously. That is, for the self aligned contact method, thick double spacers are formed on the sidewalls of the gate electrode to ensure the processing margin while forming the contact hole. On the other hand, for the borderless contact method, an etch stopping layer is formed on the whole surface of the semiconductor substrate before forming the interlayer dielectric, which prevents the field oxide layer from being etched. If both the self aligned contact method and the borderless contact method are applied simultaneously, the etch stopping layer might completely fill an interval between gate electrodes.
Therefore, the etching process to form the contact hole is implemented until the surface of the semiconductor substrate near the boundary of the active region and field region is completely exposed in order to form a contact hole of the borderless contact. However, the surface of the semiconductor substrate between the gate electrodes on which the contact hole is to be formed is not completely exposed and the contact hole is not completely opened. Otherwise, when the etching process forming the contact hole proceeds until the surface of the semiconductor substrate on which the contact hole is to be formed between the gate electrodes is exposed, the surface of the semiconductor substrate on which the contact hole is to be formed at the boundary of the active region and the field region is excessively etched.
The present invention is therefore directed to a method of forming contact holes of a semiconductor device which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present invention is to provide a method of forming contact holes of a semiconductor device in which damage at a field oxide layer of the semiconductor device can be prevented and in which processing yield can be increased.
Another object of the present invention is to provide a method of forming contact holes of a semiconductor device in which a self aligned contact method and a borderless contact method can be applied simultaneously, so that a manufacturing process of a device can be simplified.
To accomplish these objects, a method of forming contact holes of a semiconductor device is provided in the present invention. First, a plurality of gate electrodes provided with a plurality of spacers are formed on an active region of a semiconductor substrate which is separated into the active region and a field region by a field oxide layer. Then, the outermost spacers are removed from the plurality of spacers in order to ensure a space for forming a first contact hole on the semiconductor substrate. Next, an etch stopping layer and an interlayer dielectric are subsequently formed on the semiconductor substrate. By subsequently etching the interlayer dielectric and the etch stopping layer, the first contact hole is formed by exposing a first surface of the semiconductor substrate between the gate electrodes and a second contact hole is formed by exposing simultaneously a second surface of the semiconductor substrate which includes a portion of a surface of the field oxide layer and a portion of the semiconductor substrate near the field oxide layer.
According to the present invention, a manufacturing process of a DRAM device can be simplified by forming contact holes simultaneously with a self aligned contact method in which the first contact hole is formed by using a plurality of spacers and with a borderless contact method in which the second contact hole is formed from a side portion of the gate electrode to a portion of a field region. This result can be obtained by forming a plurality of gate electrodes having a plurality of spacers to form an LDD structure, by removing the outermost spacers to ensure a space for forming a first contact hole between the gate electrodes and then by forming an etch stopping layer to prevent a field region and an interlayer dielectric from being etched.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.